About:

Advanced Architectures (A2) provides Intellectual Property (IP) cores for use in ASICs, SoCs and FPGAs. We also provide architecture and design services to build chips, boards and complete systems.

We have been in business for over 20 years providing architecture, design services and IP products to the ASIC and FPGA design community.

We are unique as a design house by being able to provide a leadership role in the development of complete systems from concept through manufacturing. A2’s proficient interfacing with sales, marketing, manufacturing, and finance ensures corporate success. A2’s design experience includes implementing structured design methodologies, performing HDL modeling simulation, performance analysis, logical design, packaging and detailed implementation.

Services:

Can't find exactly what you are looking for? Advanced Architectures can help.

We can create a core, a chip, or a complete system for you, individually designed to the highest standard of craftsmanship, that perfectly matches your needs.

Every aspect of your bespoke design will be cut and tailored uniquely to your specifications. Like any private commission, having anything custom-made to your specifications requires meticulous attention to detail. With our advice you can establish all the finer points of detail that determines your own requirements and creates a design made precisely to fit in your product.

Our typical involvement in a project begins as soon as possible so that our experience in the project definition stage and system architecture development can be brought-to- bear. We strongly recommend, and always follow, a strong top-down design and development methodology that produces detail system and block-level specifications, timings and block diagrams before detailed design work begins. Our experience has shown many times that this methodology is the optimal path to a successful product in the minimal time.

Advanced Architectures has considerable experience in interfacing the development team with corporate management and providing liaison between marketing, sales, manufacturing and finance to ensure corporate success.

Our design and development services can be procured on a retainer only basis so that we can provide the best Quality of Service to our customers.

Advanced Architectures

since 1993

News :

Now available is our IoT solution. We can create a microcontroller for deeply embedded IoT systems to rapidly deploy a system to your specification.

Contact us for details

Our Bitcoin pipeline is now available as an ultra low-power two dimensional pipe. We are also converting to a self timed system to lower power even further.

Contact us for details

Products :	<click for datasheet>

Systems:

SSM: SoC System Manager is a hardware-software “subsystem” IP which decouples SoC system management functions, such as power, security, error recovery, and boot sequencing, from the specific design, and consolidates these tasks, promoting high reuse and faster hardware-software integration. Add SSM virtualization to your SoC architecture and save time and money.

A2M : IoT configurable Microcontroller is an A2P3 with a configurable collection of other A2 IP in a ready-built framework ready to be deployed in an SoC.

Processor:

A2P3 : Application Adaptive Processor is flexible processor architecture based on innovative “fine-grain” microarchitecture configurability and an expandable instruction set. The flexibility of A2P enables a basic architecture to be developed for low power applications. Available with secure debug interface, breakpoint modules and jumptrace mechanism. A complete toolset and IDE is available from ADVEDA.

Interconnect:

A2B: A high performance SoC interconnect system designed for use in synthesizable designs. It is specifically developed to meet the challenges of multiprocessor and multiple DMA / IO processor designs. A2B is designed to have the highest possible occupancy so that the sustainable bus bandwidth closely approaches the available peak bandwidth of a given configuration.

A2R : A Register interconnect mechanism between control registers in an ASIC design and any number of control devices; CPUs, debug ports etc.. The bus is especially suited for synthesizable designs. It is specifically developed to meet the challenges of long interconnect delays in large System-on-chip designs and can be tailored to match system clock rates.

Queue Manager:

A2Q : The Queue Manager creates and maintains queues in memory for use in interprocess communication and I/O device communication with processors in a system. It is capable of multiple queue coalescence and prioritization. These features provide significant performance improvement especially in multiprocessor applications or even single processor systems with multiple I/O mechanisms. In many applications the use of an RTOS can be avoided altogether freeing-up CPU cycles to do application work.

Floating Point:

A2F3 : Single Precision IEEE-754 complete FPU with available direct connect to A2P3.

A2FD : Double & Single Precision IEEE-754 complete FPU with available direct connect to A2P3. 

A2FH : Half Precision IEEE-754R complete FPU for graphics processing.

A2FM : Very high performance IEEE-754 modules.

Pipeline Stages:

A2_pipe: Stallable pipeline stage with protocol for multiway pipeline fork and join capability A2_1toNpipe: Stallable pipeline stage with width expansion

A2_Nto1pipe: Stallable pipeline stage with width contraction

FIFOs:

A2_sFIFO: Synchronous FIFO with configurable flags and counts A2_aFIFO: Asynchronous FIFO with configurable flags and counts A2_CAM_FIFO: Searchable Synchronous FIFO

A2_RW_FIFO: Synchronous FIFO with second read/write port as companion to A2_CAM_FIFO

Peripherals:

A2_EN	Ethernet MAC
A2_NF	NAND Flash Controller
A2_usart	USART
A2_timer	Timer
A2_interval	Interval Counter
A2_GPIO	General Purpose Input/Output

Others:

A2_MULT:	Configurable Multiplier, signed/unsigned with variable width and depth
A2_DIV:	Integer Dividers, signed / unsigned radix 2 or radix 4 sequential algorithm
A2_SqRt:	Integer Square Root
A2_priority:	Leading/Trailing bit position or most significant signed bit
A2_popcount:	Population Count provides the number of bits set in the input word