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A2M2 Memory Security Unit Technical Summary: A2MSU_technical_summary.pdf The A2MSU is a Memory Security Unit designed to support CPUs, DMAs, etc., that do not require a full virtual memory system, but do need to protect regions of memory from errant access by any address generating device. The A2MSU uses a register block that divides system memory into a configurable number of regions and provides each region with a set of capabilities that define what kind of accesses may be made to each region. The CPU is only responsible for loading the primary table with address boundaries and region capabilities in supervisor mode. The A2MSU may be configured as a dual system to support Harvard architecture machines with separate instruction and data paths.
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