A2 Product 2

A2B System-on-Chip Interconnect

Technical Summary: A2B_technical_summary.pdf

Application Note: A2B_application_note.pdf

Revision 2.0 Now Available

This System Bus is a high-performance mechanism intended for the interconnection of CPUs, I/O processors or other bus masters and system memories. Versions of this bus are available for System-on-Chip, Chip-to-Chip and System level applications. Current implementations in 0.18um and 0.13um ASICs are running at least 5 GB/s per bus segment. Multiple segments and and crossbar modes are available. One licensee is running over 25 GB/s of on-chip bandwidth.

MAJOR FEATURES :

	8-bit through any power of 2 data width
	8-bit through any power of 2 virtual address mode for initiators
	8-bit through any power of 2 physical address mode for initiators and targets
	Clock rate is implementation dependant
	Fully synchronous operation
	Multiple byte and burst mode data transfers
	Split transaction mode for high bus occupancy
	Split read/write bus mode for high performance

AVAILABLE EXTENSIONS :

	Parity protection on any or all buses
	Multiprocessing protocols -- including cache coherency
	Virtual addressing and translation
	Address burst / Complex addressing
	Error and Retry protocols
	Additional User-defined bus fields

The A2B synchronous system bus is a set of protocols and methodologies designed to ease the development of specific implementations of a system bus. The techniques can be applied to any level of design; that is they are equally applicable to backplane interconnect, chip-to-chip interconnect within a PCB or on-chip interconnection of major blocks.

The A2B defines the base protocols of the system and describes variations that can be applied to different implementations. Interchangeability between specific implementations of the A2B is NOT a goal of the protocols. Rather it is intended to ensure that a specific implementation performs reliably and consistently with minimal new design. The intent is to provide a core bus mechanism between the various modules of a system and the interface to the bus of each module takes care of any protocol mismatches between the module and this system bus. Each implementation must be adapted, with particular attention to the electrical, physical and temporal characteristics, to the target technologies with special consideration to issues of wiring distances, clock skew, noise and capacitance.

Versions of this bus have been successfully used for backplane buses and for an on-chip system bus for multiprocessor System-on-chip applications.

An example application uses 128-bit data buses, 64-bit physical addressing with three levels of arbitration supporting multiple CPUs, intelligent I/O controllers and memory interfaces.

[ Home ] [ Up ] [ Bespoke ] [ Company ] [ News ] [ Contact ] [ Search ]

Hit Counter