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Enhanced A2FP IEEE Floating-Point Unit
Advanced Architectures announces the availability of its enhanced A2FP IEEE Floating-Point Unit. This upgraded version supports low-latency, high performance, pipelined floating-point arithmetic. Full IEEE compliance is now supported with a dynamic pipelining technique that enables the A2FP to support clock rates of multiple Giga-Hertz, foundry dependant (of course), with only a 4-stage pipeline. Further the A2FP can now be easily configured to support multiple independent pipelines each with its own selection of floating-point operations. This allows support for multiple instruction issue per cycle as well as chaining to support parallel and vector operations. The A2FP is supplied either as an execution unit to support integration into embedded processors or combined with the A2P to create a co-processor that provides standalone engines that can be tightly or loosely coupled to other processors in a system. Typical applications include XML processing, FFT engines, high-performance GPS as well as general purpose scientific number crunching.
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